Over the last decade, CMOS Image Sensor (CIS) technology has made impressive progress. Image sensor performance has dramatically improved over the years, especially with the addition of DRAM and 3-layer stacking. By leveraging our platform to replace standard DRAM, we can add AI capabilities within the CIS itself further increasing overall performance, functionality, and efficiency.
Rolling shutter distortion
Conventional CMOS image sensor (CIS) chips collect the signal data from the pixels and send it through the logic circuit and out through the interface serially. This inherently restricts the CIS chip speed to the output speed of the interface which in turn means that the pixel reading speed is also capped at that speed. The difference in read time from the first pixel to the last results in the rolling shutter effect. For example, consider situations such as with moving objects in the picture. By the time the last pixel is read, the object may have moved some distance. This effect results in the object appearing to be swept back.
CONVENTIONAL CIS @ 30 FPS
Using DRAM to temporarily dump the pixel data onto, the interface read speed is decoupled from the pixel read speed. The New 3-layer Stacked CIS chip has pixel reading speed increased by up to 120 fps.
NEW CIS @ 120 FPS
A Pixel/DRAM/logic 3-layer stacked CIS
- The pixel, DRAM and logic wafers are manufactured using 90nm, 30nm and 40nm processes, respectively.
- The DRAM wafer and the logic wafer are joined together, and the thickness of the DRAM wafer is reduced to 3μm
- The DRAM and logic wafers are electrically connected with TSVs
- The stacked wafers of the DRAM and logic are joined to the pixel wafer
- The 3-layer wafer stack is thinned down to 130um and connected with TSVs
The numbers of TSVs connecting the pixel layer with DRAM is ~15,000 and DRAM with logic layer is ~20,000. Both of the TSVs have a diameter of 2.5μm and a pitch of 6.3μm. The 1/2.3-inch sensor has a resolution of 21.3MP and pixel size of 1.22um.
- Adding DRAM as a buffer can enhance readout speed, eliminating rolling shutter effect
- Cost effective hybrid bonding vs existing package schemes (TSV+TSV / TSV+micro-bumping)
- 2-layer stacked CIS can match 3-layer stacked CIS performance
- Integrating ADC + pre-processor into DRAM can further reduce latency
- Computer Vision and other advanced AI functionality can be built directly into DRAM